Two types of magnetoresistive random access memory (MRAM) cells including magnetic tunnel junctions (MTJ) memory elements will be described as examples of devices that can be used with the method of the invention. FIG. 1A illustrates an MRAM cell 10H which is designed for in-plane magnetization of the MTJ layer structure 200 with respect to the film surface. The MTJ 200 in this example includes a free magnetic layer 11, a nonmagnetic spacer or junction layer 12, a reference magnetic layer 13, an antiferromagnetic exchange coupling layer 14, a pinned magnetic layer 15 and an antiferromagnetic layer 16. An MRAM cell structure typically includes a top metal contact 21 and a bottom metal contact 22. The metal contacts are also referred to as electrodes. The reference magnetic layer 13 is antiferromagnetically exchange coupled to the pinned magnetic layer 15, which has a fixed magnetization direction. The free magnetic layer has a magnetization direction that is switchable in either of two directions. The resistivity of the whole MTJ layer stack changes when the magnetization of the free layer changes direction relative to that of the reference layer, exhibiting a low resistance state when the magnetization orientation of the two ferromagnetic layers is substantially parallel and a high resistance when they are anti-parallel. Therefore, the cells have two stable states that allow the cells to serve as non-volatile memory elements.
The MRAM cells in an array on a chip are connected by metal word and bit lines (not shown). Each memory cell is connected to a word line and a bit line. The word lines connect rows of cells, and bit lines connect columns of cells. Typically CMOS structures 24 include a selection transistor which is electrically connected to the MTJ stack through the top or bottom metal contacts. The direction of the current flow is between top or bottom metal contacts.
Reading the state of the cell is achieved by detecting whether the electrical resistance of the cell is in the high or low state. Writing the cells requires a sufficiently high DC current flowing in the direction through the MTJ stack between the top and bottom metal contacts to induce a spin transfer torque that orients (switches) the free layer into the desired direction. The amount of current needed to write the cells is at least slightly higher than the current that flows during the read process, so that a read operation does not change the state of the cell.
FIG. 1B illustrates another type of MRAM cell 10P which is designed for perpendicular magnetization of the MTJ layer structure 200P with respect to the film surface, but otherwise the discussion above of the in-plane example of FIG. 1A can be applied to the perpendicular MTJ example. The example of FIG. 1B does not include antiferromagnetic layer 16.
FIG. 1A and FIG. 1B show example structures of the in-plane and perpendicular MTJ structures used in MRAM devices. However, the novel method as disclosed by this invention can apply to other in-plane and perpendicular MTJ structures, as long as there is a magnetic storage (free) layer and a magnetic reference layer in such structures, without being limited to FIG. 1A and FIG. 1B structures.
Functional MRAM devices are tested by writing and reading selected patterns in the memory similar to other memory devices. Unlike older memory devices MRAM integrated circuits are susceptibility to external magnetic fields. A method of testing MRAM integrated circuits for susceptibility to external magnetic fields is described in a Freescale Semiconductor Application Note AN3525 Rev. 0, November 2007 by Jason Janesky. The magnetic fields are generated by a quadruple magnet capable of producing magnetic fields of several hundred gauss in any direction within the plane of the part being tested. A Helmholtz coil pair is also used to generate a magnetic field perpendicular to the part. Performance of the MRAM parts is measured versus applied field during part operation and after application of external fields. Typical tests were described as including testing the part for errors while applying a field at various angles and again after returning the field to 0 gauss to determine destructive error rate. The field was increased in five gauss steps until failures were observed. Because the free layers in MRAMs are susceptible to large external magnetic fields, magnetic shielding around the whole chip may be provided.
Reducing the minimum separation or minimum critical dimension (CD) between two adjacent MRAM memory cells, such as MTJ cells, on a substrate is a priority in MRAM research and development. MRAM technology is currently being developed with minimum CD below 30 nm and even the 10 nm regime is being explored. Thermal stability of the MTJ cell tends to decrease with the size of the cells. The thermal stability of the MTJ cell can be described by the thermal stability factor (delta): Δ=KuV/kBT (where Ku is the anisotropy energy density of the storage (free) magnetic layer, V being the volume of the storage (free) magnetic layer, kB being Boltzmann constant, T being absolute temperature in Kelvin). The thermal stability factor will also be called the “delta” of the cell herein. The thermal stability factor of the cells will inevitably show larger variation across a wafer or between neighboring cells in the manufacturing process. This is partially due to the varying size of the MTJ element, which is determined by the MRAM processing procedures, and becomes a larger percentage of the final CD as the CD becomes smaller. It is also partially due to the magnetic film of the MTJ element having a smaller number of magnetic grains at smaller MTJ cell sizes that makes the free layer magnetic properties, for example anisotropy field Hk, show larger variation because the averaging effect declines with the number grains.
The larger variation of the thermal stability gives rise of the possibility of existence of both high Δ (delta) cells that are not switchable with normal program current, and low Δ cells that are easily switchable with program current but are not sufficiently stable to hold stored data as long as required. For the MRAM chip to be functional, these defective cells must be detected and screened out.
The high Δ cells are relatively easy to screen out with standard on-chip circuitry based testing methods, because they do not switch when normal programming electrical current flows through the cell. These “un-switchable” cells can be detected by writing known data patterns and reading the resulting data bits.
Identifying the low Δ cells that are switchable but unstable is more problematic using pure circuit based methods and may be impractical due to the need for a complicated test algorithm and the relatively long time required to run such a test on every cell of a production MRAM chip by pure circuit based screening method alone.
Therefore, it is desirable to have a method that efficiently screens out both high Δ and low Δ MRAM MTJ cells.